📋 Description

• End-to-end physical design: floorplanning, power planning, placement, CTS, routing, optimization
• Use Cadence Innovus for placement, CTS, routing, timing optimization, and design closure.
• Analyze timing reports and perform STA to drive timing closure.
• Collaborate with RTL/synthesis teams to resolve timing, area, power, and PD challenges.
• Support design sign-off to meet PPA targets.

🎯 Requirements

• 6–15 years hands-on experience in Physical Design / ASIC implementation.
• Strong expertise in Cadence Innovus across the physical implementation flow.
• Strong understanding of Static Timing Analysis (STA) and timing closure.
• Solid knowledge of netlist to GDSII and full PD flow (floorplanning, power, placement, CTS
• Experience debugging setup/hold violations and resolving timing/congestion issues.
• Familiarity with MMMC implementation and timing constraints; scripting skills (Tcl, Python, or