You might thrive in this role if you have:

• Extensive industry experience with recent, hands-on ownership of complex networking, packet-processing, or packet-switched interconnect RTL.
• Demonstrated networking expertise in one or more of the following: Ethernet switching, NIC/SmartNIC/DPU datapaths, network accelerators, RDMA/RoCE, InfiniBand, traffic management, or custom scale-up/scale-out transports.
• Deep expertise in Verilog/SystemVerilog and the development of clean, parameterized, production-quality RTL.
• A strong record of owning major RTL blocks or SoC subsystems from requirements and microarchitecture through tape-out and silicon bring-up.
• Experience designing queues, arbiters, schedulers, buffers, routing logic, virtual channels, credit-based flow control, congestion management, quality of service, ordering, or deadlock-avoidance mechanisms.
• Experience with relevant on-chip, chip-to-chip, or host interfaces such as AXI, CHI, CXL, PCIe, or Ethernet, alongside deeper networking or packet-datapath expertise.
• Experience designing custom networking protocols, protocol extensions, or hardware datapaths for large-scale RDMA/RoCE, HPC, or AI systems.
• Strong familiarity with RTL development and signoff flows, including lint, CDC/RDC, synthesis, formal verification, static timing analysis, power analysis, and design-for-test considerations.
• Experience collaborating with architecture, verification, physical design, firmware, performance, and post-silicon teams to deliver complex silicon.
• Strong judgment when balancing performance, power, area, schedule, verification risk, and physical implementation constraints.
• The ability to provide technical direction, mentor engineers, and drive alignment while remaining actively involved in RTL design and debugging.
• A passion for reducing complexity and improving engineering leverage through automation and pragmatic design.

Preferred Qualifications

• Experience designing packet-switched interconnect or networking datapaths for AI accelerators, GPUs, CPUs, HPC systems, NICs/SmartNICs, switch ASICs, or large-scale datacenter silicon.
• Experience addressing virtualization, isolation, RAS, telemetry, security, or memory-consistency requirements within complex networking or interconnect subsystems.
• Experience with network or NoC performance modeling, traffic simulation, emulation, FPGA prototyping, or post-silicon traffic and performance analysis.
• Experience leading architecture or RTL delivery for first-generation networking or interconnect IP in rapidly evolving silicon programs.

To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

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Background checks for applicants will be administered in accordance with applicable law, and qualified applicants with arrest or conviction records will be considered for employment consistent with those laws, including the San Francisco Fair Chance Ordinance, the Los Angeles County Fair Chance Ordinance for Employers, and the California Fair Chance Act, for US-based candidates. For unincorporated Los Angeles County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: protect computer hardware entrusted to you from theft, loss or damage; return all computer hardware in your possession (including the data contained therein) upon termination of employment or end of assignment; and maintain the confidentiality of proprietary, confidential, and non-public information. In addition, job duties require access to secure and protected information technology systems and related data security obligations.

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