The Role

We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep expertise in memory BIST and TAP controller insertion at RTL, scan insertion and ATPG, and test strategy development across digital and mixed-signal domains. You will play a critical role in ensuring high test coverage, manufacturability, and first-pass silicon success while collaborating closely with design, verification, and physical design teams.

Responsibilities

• Define and implement DFT architecture for mixed-signal SoCs, including scan, MBIST, LBIST, and boundary scan.
• Lead RTL-level DFT insertion, scan chain insertion and optimization, test point insertion, and low-power DFT methodologies.
• Own ATPG flow development and execution by generating high-quality stuck-at, transition, and path delay test patterns. Drive coverage closure and pattern optimization and debug pattern failure and silicon correlation.
• Develop and integrate DFT strategies for mixed-signal blocks, including wrapper-based approaches, and analog test interfaces and BIST solutions.
• Collaborate with RTL, DV, and PD teams to ensure clean DFT integration at RTL and gate-level, and timing and physical constraints alignment (scan reordering, compression, etc.).
• Drive DFT verification and signoff, including Scan/ATPG coverage metrics, DRC/Lint checks (DFT rule compliance), gate-level simulation and pattern validation.